Synchronous Dynamic Random Access Memory (SDRAM) Memory Controllers are used in Personal Computers and in a wide variety of electronics products, generally, where microprocessors and SDRAM are imbedded in the product to define the control features and user interface of the product. SDRAM Memory Controllers allow microprocessors to efficiently access high-speed SDRAM when running programs.
As chip manufacturers relentlessly scale down silicon process feature size, driving silicon technology towards better and better electrical and economic performance, serious signal integrity issues arise in the physical interface between chips in system applications, as clock and data rates often double with each new generation. At higher clock rates signal integrity breaks down, primarily, due to transmission line
effects in the interconnect between the memory controller chip and SDRAM chip.
Transmission line effects, which include reflections, attenuation, cross-talk and ground bounce, all play a role in degrading signal quality in the interconnect between chips. Reflections in the chip-to-chip interconnect, if not managed properly, can completely destroy signal integrity in any high-speed system.
All transmission lines have a characteristic impedance and a characteristic signal velocity which are defined by conductor geometry and dielectric constant of the insulating medium surrounding the conductors. Signal reflections propagating back and forth over transmission lines can degrade signal quality to the point of non-viability if not controlled. However, no signal reflections occur in a transmission line if the source impedance of the circuit driving one end of the transmission line and the terminating impedance of circuits at the other end of the line match the characteristic impedance of the transmission line. When using semiconductor circuits, typically CMOS (complementary metal oxide semiconductor) transistors, to drive signals off-chip onto printed circuit board (PCB) traces to be received by semiconductor circuits on other chips on the printed circuit board, significant signal reflections often occur if the receiving ends of the traces are not terminated with some impedance that closely matches the transmission line impedance.
Previously, high speed signals were driven with I/O (input/output) buffers having output impedances that were much lower than the characteristic impedance of the PCB trace. The PCB traces were terminated using fixed resistors with resistance values matching the characteristic impedance of the trace. In some applications fixed resistors were also placed in series with the driving buffer to improve signal integrity. The advent of DDR (double data rate) SDRAM drove the semiconductor industry to find ways of internalizing source and termination impedances to dispose of the fixed external resistors needed to match PCB trace impedances in these new memory systems. The incentive is always to lower costs and reduce power consumption. It was clearly demonstrated that good signal integrity can be obtained in DDR Memory systems when there is a matched termination impedance. So long as the termination absorbed the signal propagating to the end of the line, no reflections occurred. In these systems, the source impedance of the circuits driving the line were purposely made lower than the characteristic impedance of the PCB traces to produce a bigger signal swing for better noise immunity.
CMOS I/O circuits can be designed to match transmission line impedances fairly well under specific conditions but exhibit large impedance variations, often exceeding 2:1, over the full Process, Voltage and Temperature (PVT) range expected for the circuit. To counter the PVT variation, circuit designers have been building in some adjustability for the Off-Chip Drive (OCD) and the On-Die Termination (ODT).
A number of solutions for programmable output impedance are in use today notably in High-Speed Transceiver Logic (HSTL) and DDR applications. In many cases there are as few as two drive settings for output impedance control. In many cases the output impedances are not dynamically set against an impedance reference.